1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a wafer acceptance testing (WAT) method, including a use of a test key.
2. Description of Related Art
In semiconductor fabrication, a semiconductor device or an integrated circuit (IC) should be continuously tested in every step so as to maintain device quality. Usually, a testing circuit is simultaneously fabricated with a actual device so that quality of the actual device can be judged by a performance of the testing circuit. The quality of the actual device therefore can be well controlled.
A typical method to test a wafer is called a wafer acceptance testing (WAT) method, which can measure defects of the wafer. The WAT method includes providing several test keys distributed in a periphery region of a die, which is desired to be tested. The test keys typically are formed on a scribe line between dies, and are electrically coupled to an external terminal through a metal pad. A module of the test keys is selected and each test key off the selected module is respectively used for a test of different property of the wafer, such as threshold voltage (V.sub.TH) or saturate current I.sub.DSAT. A controlled bias is applied to the test keys, and the induced current is read out to detect defects on the wafer.
FIG. 1 is a top view of a wafer, schematically illustrating a typical structure of a wafer. In FIG. 1, several dies 102 are formed on a wafer 101 with a matrix distribution. A scribe line 104 is naturally formed between dies 102. In each of dies 102, an actual device, including, for example metal-oxide semiconductor (MOS) transistors, capacitors, and interconnects, is formed. In semiconductor fabrication, every process is performed on the whole wafer 101 so that several testing circuits, each of which is similar to the actual device in each of the dies 102, are also simultaneously formed in the scribe line 104. The testing circuits are electrically coupled to an external read out circuit through several metal pads 106. Each pad serves as a testing key 106 for a test of a property desired to be tested. Thus, the test keys 106 are distributed on the wafer 101 and are user to test the wafer. The is a typical WAT method.
Most of device damages or wafer defects in fabrication usually result from plasma processes. Unfortunately, plasma processes are very essential in semiconductor fabrication, such dry etching or doping processes. During the plasma processes, the wafer is bombard by energetic ions and results in a damage. In addition, since the plasma ions carry a lot of charges, it may also cause a damage to the wafer due to statistic charge accumulation. For example, energetic plasma ions can penetrate through a gate to cause a damage to the gate, and further leave their charges inside the gate. Those charges from ions are accumulated by a gate oxide layer, resulting in a degradation of its isolation performance. A device current leakage is therefore induced. All these kinds of damage resulting from plasma processes are called a plasma process induced damage (P2ID).
FIG. 2 is a cross-sectional view of a portion of a substrate, schematically illustrating a structure of a conventional test key. In FIG. 2, there is a substrate 200. A testing structure 202, such as a transistor or a capacitor, is formed on the substrate 200. An inter-layer dielectric layer 204 is formed over the substrate 200 is isolate the testing structure 202. An interconnecting structure 206 is formed on the inter-layer dielectric layer 204. The interconnecting structure 206, as usual, includes interconnecting metal layer 208 and inter-metal dielectric layer 210. A metal pad layer 212 is formed on the interconnecting structure 206. A passivation layer 214 is on the top. The testing structure 202 is coupled to the interconnecting metal layer 208 through, usually, a contact. Again through a via, the interconnecting metal layer 208 is coupled to the metal pad layer 212. Desired testing signals can be obtained by reading signals at the metal pad layer 212.
The structure of the test key shown in FIG. 2 is simultaneously formed while the actual devices in each die are formed on the substrate 200 at other portion, such as the structure shown in FIG. 1. The formation of the test key includes several plasma processes. If there is any damage occurring, it can only tell that the actual device may also damage. It is difficult to clearly pin down where the damage is. Device performance defect may result from the damage of the testing structure 202, the interconnecting structure 206, or others. Engineers need to spend a lot of time to check every steps to find out which steps may cause damage. This is time consuming and causes a degradation of throughput.